`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:52:10 09/27/2011
// Design Name:   REG_ALU_LOGIC
// Module Name:   C:/Users/Chase/16bitcpu/LCD_FibonauchiSEQ_TEST_ALU-REG.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: REG_ALU_LOGIC
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module LCD_FibonauchiSEQ_TEST_ALU-REG;

	// Outputs
	wire ;

	// Instantiate the Unit Under Test (UUT)
	REG_ALU_LOGIC uut (
		.()
	);

	initial begin
		// Initialize Inputs

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

